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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
Registers
6. When DQ5 is set to 1, a READ/RESET command must be issued before any subsequent
command.
Table 8: Operations and Corresponding Bit Settings
Note 1 applies to entire table
Operation
PROGRAM
BLANK CHECK
CHIP ERASE
BLOCK ERASE
before time-out
BLOCK ERASE
Address
Any address
Any address
Any address
Erasing block
Non-erasing block
Erasing block
Non-erasing block
DQ7
DQ7#
1
0
0
0
0
0
DQ6
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ5
0
0
0
0
0
0
0
DQ3
–
–
1
0
0
1
1
DQ2
–
–
Toggle
Toggle
No toggle
Toggle
No toggle
DQ1
0
0
–
–
–
–
–
RY/BY#
0
0
0
0
0
0
0
Notes
2
PROGRAM
SUSPEND
Programming
block
Nonprogramming
Invalid operation
Outputs memory array data as if in read mode
High-Z
High-Z
block
ERASE
Erasing block
1
No Toggle
0
–
Toggle
–
High-Z
SUSPEND
Non-erasing block
Outputs memory array data as if in read mode
High-Z
PROGRAM during
ERASE SUSPEND
BUFFERED
Erasing block
Non-erasing block
Any address
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
0
0
0
–
–
–
Toggle
No Toggle
–
–
–
1
0
0
High-Z
2
2
PROGRAM ABORT
PROGRAM Error
ERASE Error
BLANK CHECK Er-
Any address
Any address
Any address
DQ7#
0
1
Toggle
Toggle
Toggle
1
1
1
–
1
1
–
Toggle
Toggle
–
–
–
High-Z
High-Z
High-Z
2
ror
Notes:
1. Unspecified data bits should be ignored.
2. DQ7# for buffer program is related to the last address location loaded.
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. B 8/12 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2012 Micron Technology, Inc. All rights reserved.
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